1. Technical Field
The present disclosure generally relates to information handling systems and in particular to a system and method for improving peripheral component interface express bus performance in an information handling system.
2. Description of the Related Art
As the value and use of information continue to increase, individuals and businesses seek additional ways to process and store information. One option available to users is information handling systems. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal or other purposes, thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
Peripheral component interconnect express (PCIe) is a local serial expansion bus for attaching hardware devices in an information handling system. The attached hardware devices can be a wide variety of devices, including, but not limited to, co-processors, graphic processing units (GPUs) and storage devices, such as solid state storage devices (SSD). The PCIe bus supports the functions found on a processor bus, but in a standardized format that is independent of any particular processor's native bus. PCIe is based on point-to-point topology, with separate serial links connecting every device to the host. A PCIe bus link supports full-duplex communication between any two endpoints, with no inherent limitation on concurrent access across multiple endpoints. PCIe communications are encapsulated in packets. The work of packetizing and de-packetizing data and status-message traffic is handled by the transaction layer of the PCIe port.
One problem with current information handling systems is that the PCIe bus includes several PCIe endpoints that can utilize and/or manipulate data from the same physical/machine memory address. A duplication of upstream and downstream transactions can occur, resulting in increased data transmission times and latency. The duplication of transactions reduces the PCIe bandwidth capacity and increases system latency.